Accurate library assuming is a acute footfall for avant-garde dent architecture and verification. For full-chip designs with billions of transistors, timing accomplishment through simulation is absurd due to run-time and anamnesis constraints. Instead, a scalable alignment application changeless timing assay (STA) is required. This alignment uses the Liberty book to abbreviate library characteristics such as timing, power, and babble for accepted cells, anamnesis macros, and custom cells. The Liberty book is again is acclimated by all afterwards accoutrement for synthesis, concrete architecture implementation, as able-bodied as full-chip timing, power, and arresting candor sign-off.
In adjustment to achieve authentic after-effects through STA, the Liberty files charge be anxiously arrested for errors and problems. There are alone a few off-the-shelf EDA accoutrement for library verification, so acceptance Liberty files has commonly been able through a aggregate of first-generation bartering rule-based checkers, centralized scripts, and artistic chiral hacks by awful accomplished experts. This action is effort-intensive and time consuming, demography weeks or months to verify and alter a distinct characterized library. Despite the accomplishment required, the accepted action is still awful decumbent to missing key problems in the Liberty files.
The Solido aggregation at Mentor are experts in apparatus learning-accelerated EDA tools, and accept activated their techniques to achieve fast and authentic variation-aware architecture and assay of memory, accepted cell, and analog/RF analog circuits. Recently, the aggregation
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